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HFA3101
Data Sheet September 1998 File Number 3663.4
Gilbert Cell UHF Transistor Array
The HFA3101 is an all NPN transistor array configured as a Multiplier Cell. Based on Intersil's bonded wafer UHF-1 SOI process, this array achieves very high fT (10GHz) while maintaining excellent hFE and VBE matching characteristics that have been maximized through careful attention to circuit design and layout, making this product ideal for communication circuits. For use in mixer applications, the cell provides high gain and good cancellation of 2nd order distortion terms.
Features
* High Gain Bandwidth Product (fT) . . . . . . . . . . . . . 10GHz * High Power Gain Bandwidth Product . . . . . . . . . . . . 5GHz * Current Gain (hFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 * Low Noise Figure (Transistor). . . . . . . . . . . . . . . . . . 3.5dB * Excellent hFE and VBE Matching * Low Collector Leakage Current . . . . . . . . . . . . . . <0.01nA * Pin-to-Pin Compatible to UPA101
Ordering Information
PART NUMBER (BRAND) HFA3101B (H3101B) HFA3101B96 (H3101B) TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 8 Ld SOIC 8 Ld SOIC Tape and Reel PKG. NO. M8.15 M8.15
Applications
* Balanced Mixers * Multipliers * Demodulators/Modulators * Automatic Gain Control Circuits * Phase Detectors
Pinout
HFA3101 (SOIC) TOP VIEW
8 7 6 5
* Fiber Optic Signal Processing * Wireless Communication Systems * Wide Band Amplification Stages * Radio and Satellite Communications * High Performance Instrumentation
Q1 Q2 Q5 1 2 Q3 Q4 Q6 3 4
NOTE: Q5 and Q6 - 2 Paralleled 3m x 50m Transistors Q1, Q2, Q3, Q4 - Single 3m x 50m Transistors
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HFA3101
Absolute Maximum Ratings
VCEO, Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . 8.0V VCBO, Collector to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . 12.0V VEBO, Emitter to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V IC, Collector Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC (NOTE 2) TEST LEVEL A A A A A A C ALL GRADES MIN 12 8 5.5 40 VEB = 0, f = 1MHz B IC = 10mA, VCE = 5V IC = 20mA, VCE = 5V IC = 10mA, VCE = 5V IC = 20mA, VCE = 5V IC = 5mA, VCE = 3V IC = 5mA, VCE = 3V IC = 5mA, VCE = 3V f = 0.5GHz f = 1.0GHz f = 0.5GHz f = 1.0GHz f = 0.5GHz f = 1.0GHz C C C C C C C C C C A A A C B 0.9 TYP 18 12 6 0.1 70 0.300 0.600 0.200 0.400 10 10 5 5 17.5 11.9 1.7 2.0 2.25 2.5 1.0 1.5 5 0.5 0.01 MAX 10 200 1.1 5 25 mV A V/oC nA pF pF pF pF GHz GHz GHz GHz dB dB dB dB dB dB UNITS V V V nA nA
PARAMETER Collector-to-Base Breakdown Voltage, V(BR)CBO, Q1 thru Q6 Collector-to-Emitter Breakdown Voltage, V(BR)CEO, Q5 and Q6 Emitter-to-Base Breakdown Voltage, V(BR)EBO, Q1 thru Q6 Collector Cutoff Current, ICBO, Q1 thru Q4 Emitter Cutoff Current, IEBO, Q5 and Q6 DC Current Gain, hFE, Q1 thru Q6 Collector-to-Base Capacitance, CCB Q1 thru Q4 Q5 and Q6 Emitter-to-Base Capacitance, CEB Q1 thru Q4 Q5 and Q6 Current Gain-Bandwidth Product, fT Q1 thru Q4 Q5 and Q6 Power Gain-Bandwidth Product, fMAX Q1 thru Q4 Q5 and Q6 Available Gain at Minimum Noise Figure, GNFMIN, Q5 and Q6 Minimum Noise Figure, NFMIN, Q5 and Q6
TEST CONDITIONS IC = 100A, IE = 0 IC = 100A, IB = 0 IE = 10A, IC = 0 VCB = 8V, IE = 0 VEB = 1V, IC = 0 IC = 10mA, VCE = 3V VCB = 5V, f = 1MHz
50 Noise Figure, NF50, Q5 and Q6
DC Current Gain Matching, hFE1/hFE2, Q1 and Q2, Q3 and Q4, and Q5 and Q6 Input Offset Voltage, VOS, (Q1 and Q2), (Q3 and Q4), (Q5 and Q6) Input Offset Current, IC, (Q1 and Q2), (Q3 and Q4), (Q5 and Q6)
IC = 10mA, VCE = 3V IC = 10mA, VCE = 3V IC = 10mA, VCE = 3V
Input Offset Voltage TC, dVOS/dT, (Q1 and Q2, Q3 and Q4, IC = 10mA, VCE = 3V Q5 and Q6) Collector-to-Collector Leakage, ITRENCH-LEAKAGE VTEST = 5V
NOTE: 2. Test Level: A. Production Tested, B. Typical or Guaranteed Limit Based on Characterization, C. Design Typical for Information Only.
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HFA3101 PSPICE Model for a 3 m x 50 m Transistor
.Model NUHFARRY NPN
+ (IS = 1.840E-16 + VAR = 4.500E+00 + IKF = 5.400E-02 + NC = 1.800E+00 + MJC = 2.400E-01 + MJE = 5.100E-01 + ITF = 3.500E-02 + XCJC = 9.000E-01 + RE = 1.848E+00 + AF = 1.000E+00) XTI = 3.000E+00 BF = 1.036E+02 XTB = 0.000E+00 IKR = 5.400E-02 VJC = 9.700E-01 VJE = 8.690E-01 XTF = 2.300E+00 CJS = 1.689E-13 RB = 5.007E+01 EG = 1.110E+00 ISE = 1.686E-19 BR = 1.000E+01 RC = 1.140E+01 FC = 5.000E-01 TR = 4.000E-09 VTF = 3.500E+00 VJS = 9.982E-01 RBM = 1.974E+00 VAF = 7.200E+01 NE = 1.400E+00 ISC = 1.605E-14 CJC = 3.980E-13 CJE = 2.400E-13 TF = 10.51E-12 PTF = 0.000E+00 MJS = 0.000E+00 KF = 0.000E+00
Common Emitter S-Parameters of 3 m x 50 m Transistor
FREQ. (Hz) |S11| PHASE(S11) |S12| PHASE(S12) |S21| PHASE(S21) |S22| PHASE(S22) VCE = 5V and IC = 5mA 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 1.1E+09 1.2E+09 1.3E+09 1.4E+09 1.5E+09 1.6E+09 1.7E+09 1.8E+09 1.9E+09 2.0E+09 2.1E+09 2.2E+09 2.3E+09 2.4E+09 2.5E+09 2.6E+09 2.7E+09 0.83 0.79 0.73 0.67 0.61 0.55 0.50 0.46 0.42 0.39 0.36 0.34 0.32 0.30 0.28 0.27 0.25 0.24 0.23 0.22 0.21 0.20 0.20 0.19 0.18 0.18 0.17 -11.78 -22.82 -32.64 -41.08 -48.23 -54.27 -59.41 -63.81 -67.63 -70.98 -73.95 -76.62 -79.04 -81.25 -83.28 -85.17 -86.92 -88.57 -90.12 -91.59 -92.98 -94.30 -95.57 -96.78 -97.93 -99.05 -100.12 1.41E-02 2.69E-02 3.75E-02 4.57E-02 5.19E-02 5.65E-02 6.00E-02 6.27E-02 6.47E-02 6.63E-02 6.75E-02 6.85E-02 6.93E-02 7.00E-02 7.05E-02 7.10E-02 7.13E-02 7.17E-02 7.19E-02 7.21E-02 7.23E-02 7.25E-02 7.27E-02 7.28E-02 7.29E-02 7.30E-02 7.31E-02 78.88 68.63 59.58 51.90 45.50 40.21 35.82 32.15 29.07 26.45 24.19 22.24 20.53 19.02 17.69 16.49 15.41 14.43 13.54 12.73 11.98 11.29 10.64 10.05 9.49 8.96 8.47 11.07 10.51 9.75 8.91 8.10 7.35 6.69 6.11 5.61 5.17 4.79 4.45 4.15 3.89 3.66 3.45 3.27 3.10 2.94 2.80 2.68 2.56 2.45 2.35 2.26 2.18 2.10 168.57 157.89 148.44 140.36 133.56 127.88 123.10 119.04 115.57 112.55 109.91 107.57 105.47 103.57 101.84 100.26 98.79 97.43 96.15 94.95 93.81 92.73 91.70 90.72 89.78 88.87 88.00 0.97 0.93 0.86 0.79 0.73 0.67 0.62 0.57 0.53 0.50 0.47 0.45 0.43 0.41 0.40 0.39 0.38 0.37 0.36 0.35 0.35 0.34 0.34 0.33 0.33 0.33 0.33 -11.05 -21.35 -30.44 -38.16 -44.59 -49.93 -54.37 -58.10 -61.25 -63.96 -66.31 -68.37 -70.19 -71.83 -73.31 -74.66 -75.90 -77.05 -78.12 -79.13 -80.09 -80.99 -81.85 -82.68 -83.47 -84.23 -84.97
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HFA3101 Common Emitter S-Parameters of 3 m x 50 m Transistor
FREQ. (Hz) 2.8E+09 2.9E+09 3.0E+09 |S11| 0.17 0.16 0.16 PHASE(S11) -101.15 -102.15 -103.11 |S12| 7.31E-02 7.32E-02 7.32E-02 PHASE(S12) 8.01 7.57 7.16 |S21| 2.02 1.96 1.89 (Continued) PHASE(S21) 87.15 86.33 85.54 |S22| 0.33 0.33 0.33 PHASE(S22) -85.68 -86.37 -87.05
VCE = 5V and IC = 10mA 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 1.1E+09 1.2E+09 1.3E+09 1.4E+09 1.5E+09 1.6E+09 1.7E+09 1.8E+09 1.9E+09 2.0E+09 2.1E+09 2.2E+09 2.3E+09 2.4E+09 2.5E+09 2.6E+09 2.7E+09 2.8E+09 2.9E+09 3.0E+09 0.72 0.67 0.60 0.53 0.47 0.42 0.37 0.34 0.31 0.29 0.27 0.25 0.24 0.22 0.21 0.20 0.20 0.19 0.18 0.18 0.17 0.17 0.16 0.16 0.16 0.15 0.15 0.15 0.15 0.14 -16.43 -31.26 -43.76 -54.00 -62.38 -69.35 -75.26 -80.36 -84.84 -88.83 -92.44 -95.73 -98.75 -101.55 -104.15 -106.57 -108.85 -110.98 -113.00 -114.90 -116.69 -118.39 -120.01 -121.54 -122.99 -124.37 -125.69 -126.94 -128.14 -129.27 1.27E-02 2.34E-02 3.13E-02 3.68E-02 4.05E-02 4.31E-02 4.49E-02 4.63E-02 4.72E-02 4.80E-02 4.86E-02 4.90E-02 4.94E-02 4.97E-02 4.99E-02 5.01E-02 5.03E-02 5.05E-02 5.06E-02 5.07E-02 5.08E-02 5.09E-02 5.10E-02 5.11E-02 5.12E-02 5.12E-02 5.13E-02 5.13E-02 5.14E-02 5.15E-02 75.41 62.89 52.58 44.50 38.23 33.34 29.47 26.37 23.84 21.75 20.00 18.52 17.25 16.15 15.19 14.34 13.60 12.94 12.34 11.81 11.33 10.89 10.50 10.13 9.80 9.49 9.21 8.95 8.71 8.49 15.12 13.90 12.39 10.92 9.62 8.53 7.62 6.86 6.22 5.69 5.23 4.83 4.49 4.19 3.93 3.70 3.49 3.30 3.13 2.98 2.84 2.72 2.60 2.49 2.39 2.30 2.22 2.14 2.06 1.99 165.22 152.04 141.18 132.57 125.78 120.37 116.00 112.39 109.36 106.77 104.51 102.53 100.75 99.16 97.70 96.36 95.12 93.96 92.87 91.85 90.87 89.94 89.06 88.21 87.39 86.60 85.83 85.09 84.36 83.66 0.95 0.88 0.79 0.70 0.63 0.57 0.51 0.47 0.44 0.41 0.39 0.37 0.35 0.34 0.33 0.32 0.31 0.31 0.30 0.30 0.30 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 -14.26 -26.95 -37.31 -45.45 -51.77 -56.72 -60.65 -63.85 -66.49 -68.71 -70.62 -72.28 -73.76 -75.08 -76.28 -77.38 -78.41 -79.37 -80.27 -81.13 -81.95 -82.74 -83.50 -84.24 -84.95 -85.64 -86.32 -86.98 -87.62 -88.25
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HFA3101 Application Information
The HFA3101 array is a very versatile RF Building block. It has been carefully laid out to improve its matching properties, bringing the distortion due to area mismatches, thermal distribution, betas and ohmic resistances to a minimum. The cell is equivalent to two differential stages built as two "variable transconductance multipliers" in parallel, with their outputs cross coupled. This configuration is well known in the industry as a Gilbert Cell which enables a four quadrant multiplication operation. Due to the input dynamic range restrictions for the input levels at the upper quad transistors and lower tail transistors, the HFA3101 cell has restricted use as a linear four quadrant multiplier. However, its configuration is well suited for uses where its linear response is limited to one of the inputs only, as in modulators or mixer circuit applications. Examples of these circuits are up converters, down converters, frequency doublers and frequency/phase detectors. Although linearization is still an issue for the lower pair input, emitter degeneration can be used to improve the dynamic range and consequent linearity. The HFA3101 has the lower pair emitters brought to external pins for this purpose. In modulators applications, the upper quad transistors are used in a switching mode where the pairs Q1/Q2 and Q3/Q4 act as non saturating high speed switches. These switches are controlled by the signal often referred as the carrier input. The signal driving the lower pair Q5/Q6 is commonly used as the modulating input. This signal can be linearly transferred to the output by either the use of low signal levels (Well below the thermal voltage of 26mV) or by the use of emitter degeneration. The chopped waveform appearing at the output of the upper pair (Q1 to Q4) resembles a signal that is multiplied by +1 or -1 at every half cycle of the switching waveform.
CARRIER SIGNAL +1
Figure 1 shows the typical input waveforms where the frequency of the carrier is higher than the modulating signal. The output waveform shows a typical suppressed carrier output of an up converter or an AM signal generator. Carrier suppression capability is a property of the well known Balanced modulator in which the output must be zero when one or the other input (carrier or modulating signal) is equal to zero. however, at very high frequencies, high frequency mismatches and AC offsets are always present and the suppression capability is often degraded causing carrier and modulating feedthrough to be present. Being a frequency translation circuit, the balanced modulator has the properties of translating the modulating frequency (M) to the carrier frequency (C), generating the two side bands U = C + M and L = C - M. Figure 2 shows some translating schemes being used by balanced mixers.
C - M C
C + M
FIGURE 2A. UP CONVERSION OR SUPPRESSED CARRIER AM
IF (C - M) FOLDED BACK
M
C
-1 MODULATING SIGNAL
FIGURE 2B. DOWN CONVERSION
C
BASEBAND
DIFFERENTIAL OUTPUT
M
FIGURE 1. TYPICAL MODULATOR SIGNALS
FIGURE 2C. ZERO IF OR DIRECT DOWN CONVERSION FIGURE 2. MODULATOR FREQUENCY SPECTRUM
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HFA3101
The use of the HFA3101 as modulators has several advantages when compared to its counterpart, the diode doublebalanced mixer, in which it is required to receive enough energy to drive the diodes into a switching mode and has also some requirements depending on the frequency range desired, of different transformers to suit specific frequency responses. The HFA3101 requires very low driving capabilities for its carrier input and its frequency response is limited by the fT of the devices, the design and the layout techniques being utilized. Up conversion uses, for UHF transmitters for example, can be performed by injecting a modulating input in the range of 45MHz to 130MHz that carries the information often called IF (Intermediate frequency) for up conversion (The IF signal has been previously modulated by some modulation scheme from a baseband signal of audio or digital information) and by injecting the signal of a local oscillator of a much higher frequency range from 600MHz to 1.2GHz into the carrier input. Using the example of a 850MHz carrier input and a 70MHz IF, the output spectrum will contain a upper side band of 920MHz, a lower side band of 780MHz and some of the carrier (850MHz) and IF (70MHz) feedthrough. A Band pass filter at the output can attenuate the undesirable signals and the 920MHz signal can be routed to a transmitter RF power amplifier. Down conversion, as the name implies, is the process used to translate a higher frequency signal to a lower frequency range conserving the modulation information contained in the higher frequency signal. One very common typical down conversion use for example, is for superheterodyne radio receivers where a translated lower frequency often referred as intermediate frequency (IF) is used for detection or demodulation of the baseband signal. Other application uses include down conversion for special filtering using frequency translation methods. An oscillator referred as the local oscillator (LO) drives the upper quad transistors of the cell with a frequency called C . The lower pair is driven by the RF signal of frequency M to be translated to a lower frequency IF. The spectrum of the IF output will contain the sum and difference of the frequencies C and M. Notice that the difference can become negative when the frequency of the local oscillator is lower than the incoming frequency and the signal is folded back as in Figure 2.
NOTE: The acronyms RF, IF and LO are often interchanged in the industry depending on the application of the cell as mixers or modulators. The output of the cell also contains multiples of the frequency of the signal being fed to the upper quad pair of transistors because of the switching action equivalent to a square wave multiplication. In practice, however, not only the odd multiples in the case of a symmetrical square wave but some of the even multiples will also appear at the output spectrum due to the nature of the actual switching waveform and high frequency performance. By-products of the form M*C + N*M with M and N being positive or negative integers are also expected to be present at the output and their levels are carefully examined and minimized by the design. This distortion is considered one of the figures of merit for a mixer application.
The process of frequency doubling is also understood by having the same signal being fed to both modulating and carrier ports. The output frequency will be the sum of C and M which is equivalent to the product of the input frequency by 2 and a zero Hz or DC frequency equivalent to the difference of C and M . Figure 2 also shows one technique in use today where a process of down conversion named zero IF is made by using a local oscillator with a very pure signal frequency equal to the incoming RF frequency signal that contains a baseband (audio or digital signal) modulation. Although complex, the extraction or detection of the signal is straightforward. Another useful application of the HFA3101 is its use as a high frequency phase detector where the two signals are fed to the carrier and modulation ports and the DC information is extracted from its output. In this case, both ports are utilized in a switching mode or overdrive, such that the process of multiplication takes place in a quasi digital form (2 square waves). One application of a phase detector is frequency or phase demodulation where the FM signal is split before the modulating and carrier ports. The lower input port is always 90 degrees apart from the carrier input signal through a high Q tuned phase shift network. The network, being tuned for a precise 90 degrees shift at a nominal frequency, will set the two signals 90 degrees apart and a quiescent output DC level will be present at the output. When the input signal is frequency modulated, the phase shift of the signal coming from the network will deviate from 90 degrees proportional to the frequency deviation of the FM signal and a DC variation at the output will take place, resembling the demodulated FM signal. The HFA3101 could also be used for quadrature detection, (I/Q demodulation), AGC control with limited range, low level multiplication to name a few other applications.
Biasing
Various biasing schemes can be employed for use with the HFA3101. Figure 3 shows the most common schemes. The biasing method is a choice of the designer when cost, thermal dependence, voltage overheads and DC balancing properties are taken into consideration. Figure 3A shows the simplest form of biasing the HFA3101. The current source required for the lower pair is set by the voltage across the resistor RBIAS less a VBE drop of the lower transistor. To increase the overhead, collector resistors are substituted by an RF choke as the upper pair functions as a current source for AC signals. The bases of the upper and lower transistors are biased by RB1 and RB2 respectively. The voltage drop across the resistor R2 must be higher than a VBE with an increase sufficient to assure that the collector to base junctions of the lower pair are always reverse biased. Notice that this same voltage also sets the VCE of operation of the lower pair which is important for the optimization of gain. Resistors REE are nominally zero for applications where the input signals are well below
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HFA3101
25mV peak. Resistors REE are used to increase the linearity of the circuit upon higher level signals. The drop across REE must be taken into consideration when setting the current source value. Figure 3B depicts the use of a common resistor sharing the current through the cell which is used for temperature
VCC RC VCC RB1 LCH R1 8 7 6 5 RB1 LCH R1 7 6 5 RB1 LCH VCC
compensation as the lower pair VBE drop at the rate of -2mV/oC. Figure 3C uses a split supply.
R1
8
7
6 Q6 3 RE VEE
8
Q1 Q2 Q5 R2 1 2
Q3 Q4 Q6 R2 3 4
R2 Q1 Q2 Q5 1 2 Q3 Q4 Q6 1 3 4 Q1 Q2 Q5 2 Q3 Q4
REE RBIAS RB2
REE RBIAS RE
REE
REE RBIAS
REE
REE
RB2 RE
RB2
FIGURE 3A.
FIGURE 3B. FIGURE 3.
FIGURE 3C.
Design Example: Down Converter Mixer
Figure 4 shows an example of a low cost mixer for cellular applications.
VCC 3V LO IN 0.1 0.01 51 825MHz VCC 8 7 6 5 5p TO 12p 75MHz 0.01 110 Q1 Q2 Q5 1 2 0.01 330 Q3 Q4 Q6 3 4 RF IN LCH 390nH 2K IF OUT
The design flexibility of the HFA3101 is demonstrated by a low cost, and low voltage mixer application at the 900MHz range. The choice of good quality chip components with their self resonance outside the boundaries of the application are important. The design has been optimized to accommodate the evaluation of the same layout for various quiescent current values and lower supply voltages. The choice of RE became important for the available overhead and also for maintaining an AC true impedance for high frequency signals. The value of 27 has been found to be the optimum minimum for the application. The input impedances of the HFA3101 base input ports are high enough to permit their termination with 50 resistors. Notice the AC termination by decoupling the bias circuit through good quality capacitors. The choice of the bias has been related to the available power supply voltage with the values of R1, R2 and RBIAS splitting the voltages for optimum VCE values. For evaluation of the cell quiescent currents, the voltage at the emitter resistor RE has been recorded. The gain of the circuit, being a function of the load and the combined emitter resistances at high frequencies have been kept to a maximum by the use of an output match network. The high output impedance of the HFA3101 permits
51 0.01 220 27
0.01 900MHz
FIGURE 4. 3V DOWN CONVERTER APPLICATION
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4
5
HFA3101
broadband match if so desired at 50 (RL = 50 to 2k) as well as with tuned medium Q matching networks (L, T etc.). setup as in Table 1. S22 characterization is enough to assure the calculation of L, T or transmission line matching networks.
TABLE 1. S22 PARAMETERS FOR DOWN CONVERSION, LCH = 10H FREQUENCY 10MHz 45MHz 75MHz 100MHz RESISTANCE 265 420 122 67 REACTANCE 615 - 735 - 432 - 320
Stability
The cell, by its nature, has very high gain and precautions must be taken to account for the combination of signal reflections, gain, layout and package parasitics. The rule of thumb of avoiding reflected waves must be observed. It is important to assure good matching between the mixer stage and its front end. Laboratory measurements have shown some susceptibility for oscillation at the upper quad transistors input. Any LO prefiltering has to be designed such the return loss is maintained within acceptable limits specially at high frequencies. Typical off the shelf filters exhibits very poor return loss for signals outside the passband. It is suggested that a "pad" or a broadband resistive network be used to interface the LO port with a filter. The inclusion of a parallel 2K resistor in the load decreases the gain slightly which improves the stability factor and also improves the distortion products (output intermodulation or 3rd order intercept). The employment of good RF techniques shall suffice the stability requirements.
TABLE 2. TYPICAL PARAMETERS FOR DOWN CONVERSION, LCH = 10H PARAMETER Power Gain TOI Output NF SSB Power Gain TOI Output NF SSB LO LEVEL -6dBm -6dBm -6dBm 0dBm 0dBm 0dBm VCC = 3V IBIAS = 8mA 8.5dB 11.5dBm 14.5dB 8.6dB 11dBm 15dB VCC = 4V IBIAS = 19mA 10dB 13dBm 20dB 11dB 12.5dBm 24dB
Evaluation
The evaluation of the HFA3101 in a mixer configuration is presented in Figures 6 to 11, Table 1 and Table 2. The layout is depicted in Figure 5.
PARAMETER Power Gain TOI Output NF SSB Power Gain TOI Output NF SSB
LO LEVEL -6dBm -6dBm -6dBm 0dBm 0dBm 0dBm
TABLE 3. TYPICAL VALUES OF S22 FOR THE OUTPUT PORT. LCH = 390nH IBIAS = 8mA (SET UP OF FIGURE 11) FREQUENCY 300MHz 600MHz 900MHz 1.1GHz RESISTANCE 22 7.5 5.2 3.9 REACTANCE -115 -43 -14 0
TABLE 4. TYPICAL VALUES OF S22. LCH = 390nH, IBIAS = 18mA FREQUENCY 300MHz 600MHz FIGURE 5. UP/DOWN CONVERTER LAYOUT, 400%; MATERIAL G10, 0.031 900MHz 1.1GHz RESISTANCE 23.5 10.3 8.7 8 REACTANCE -110 -39 -14 0
The output matching network has been designed from data taken at the output port at various test frequencies with the
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Up Converter Example
An application for a up converter as well as a frequency multiplier can be demonstrated using the same layout, with an addition of matching components. The output port S22 must be characterized for proper matching procedures and depending on the frequency desired for the output, transmission line transformations can be designed. The return loss of the input ports maintain acceptable values in excess of 1.2GHz which can permit the evaluation of a frequency doubler to 2.4GHz if so desired. The addition of the resistors REE can increase considerably the dynamic range of the up converter as demonstrated at Figure 13. The evaluation results depicted in Table 5 have been obtained by a triple stub tuner as a matching network for the output due to the layout constraints. Based on the evaluation results it is clear that the cell requires a higher Bias current for overall performance.
VCC 3V LCH 2K 4V 8 7 6 5 0.1 0dB 5dB/DIV
S11 LOG MAG
3V
Q1 Q2 Q5 1 2
Q3 Q4 Q6 3 4 100MHz 1.1GHz
FIGURE 6. OUTPUT PORT S22 TEST SET UP
FIGURE 7. LO PORT RETURN LOSS
0dB 10dB/DIV
S11 LOG MAG 0dB 5dB/DIV
S22 LOG MAG
100MHz
1.1GHz
10MHz
110MHz
FIGURE 8. RF PORT RETURN LOSS
FIGURE 9. IF PORT RETURN LOSS, WITH MATCHING NETWORK
RF = 900MHz -25dBm LO = 825MHz -6dBm
RF = 901MHz - 25dBm LO = 825MHz -6dBm 10dB/ DIV -17dBm 10dB/ DIV
-26dBm -36dBm -53dBm
64M 11*LO - 10RF
76MHz IF
88M 12RF - 13LO
SPAN 40MHz 675 750 LO - 2RF 825 900
-58dBm SPAN 500MHz 975 LO + 2RF
FIGURE 10. TYPICAL IN BAND OUTPUT SPECTRUM, VCC = 3V
FIGURE 11. TYPICAL OUT OF BAND OUTPUT SPECTRUM
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HFA3101
Design Example: Up Converter Mixer Figure 12 shows an example of an up converter for cellular applications.
TABLE 5. TYPICAL PARAMETERS FOR THE UP CONVERTER EXAMPLE PARAMETER Power Gain, LO = -6dBm Power Gain, LO = 0dBm RF Isolation, LO = 0dBm LO Isolation, LO = 0dBm VCC = 3V IBIAS = 8mA 3dB 4dB 15dBc 28dBc VCC = 4V IBIAS = 18mA 5.5dBm 7.2dB 22dBc 28dBc
Conclusion
The HFA3101 offers the designer a number of choices and different applications as a powerful RF building block. Although isolation is degraded from the theoretical results for the cell due to the unbalanced, nondifferential input schemes being used, a number of advantages can be taken into consideration like cost, flexibility, low power and small outline when deciding for a design.
VCC 3V 47-100pF 0.01 390nH 0.01 51 11p 8 7 6 VCC 0.01 110 Q1 Q2 Q5 330 1 2 Q3 Q4 Q6 0.01 3 4 RF IN 75MHz 51 3V 5 5.2nH 900MHz 0.1
LO IN 825MHz
0.01
REE 0.01 220
REE
27
FIGURE 12. UP CONVERTER
OUTPUT WITHOUT EMITTER DEGENERATION
OUTPUT WITH EMITTER DEGENERATION REE = 4.7
EXPANDED SPECTRUM REE = 4.7
890 2LO - 10RF RF = 76MHz LO = 825MHz
901
912 12RF
SPAN 50MHz
825
900
976
FIGURE 13. TYPICAL SPECTRUM PERFORMANCE OF UP CONVERTER
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HFA3101 Typical Performance Curves for Transistors
70 IB = 1mA 60 IB = 800A 50 IB = 600A IC (mA) 40 IB = 400A 30 40 20 10 0 0 10-10 0 2.0 VCE (V) 4.0 6.0 10-8 10-6 10-4 IC (A) 10-2 100 IB = 200A 20 hFE 140 VCE = 5V 120 100 80 60
FIGURE 14. IC vs VCE
FIGURE 15. HFE vs IC
100 VCE = 3V 10-2 IC AND IB (A) 10-4 10-6 10-8 10-10 10-12 0.20 fT (GHz) 0.40 0.60 VBE (V) 0.80 1.0
12 10 8 6 4 2 0 10-4
10-3 IC (A)
10-2
10-1
FIGURE 16. GUMMEL PLOT
FIGURE 17. fT vs IC
4.8 4.6 NOISE FIGURE (dB) 4.4 4.2 4.0 3.8 3.6 3.4 3.2 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz)
20 18 16 |S21| (dB) 14 12 10 8 6 4 3.0
FIGURE 18. GAIN AND NOISE FIGURE vs FREQUENCY NOTE: Figures 14 through 18 are only for Q5 and Q6.
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HFA3101 Die Characteristics
PROCESS UHF-1 DIE DIMENSIONS: 53 mils x 52 mils x 14 mils 1340m x 1320m x 355.6m METALLIZATION: Type: Metal 1: AlCu(2%)/TiW Thickness: Metal 1: 8kA 0.5kA Type: Metal 2: AlCu(2%) Thickness: Metal 2: 16kA 0.8kA PASSIVATION: Type: Nitride Thickness: 4kA 0.5kA SUBSTRATE POTENTIAL (Powered Up): Floating
Metallization Mask Layout
HFA3101
7
7
6
6
8
5
8
5
1
4
1
4
2
2
3
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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